发明名称 |
Method for manufacturing an insulated gate field effect transistor device |
摘要 |
An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature. Owing to a high segregation coefficient of arsenic in silicon dioxide, nearly all of the arsenic in the source layer is driven into extremely shallow source and drain regions which acquire high surface concentrations.
|
申请公布号 |
US4471524(A) |
申请公布日期 |
1984.09.18 |
申请号 |
US19830564368 |
申请日期 |
1983.12.23 |
申请人 |
AT&T BELL LABORATORIES |
发明人 |
KINSBRON, ELIEZER;LYNCH, WILLIAM T. |
分类号 |
H01L21/225;H01L21/28;(IPC1-7):H01L21/22 |
主分类号 |
H01L21/225 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|