发明名称 MEMORY FAULT CORRECTING SYSTEM
摘要 PURPOSE:To prevent the data processing ability from being deteriorated by changing over a mode into a memory alternate mode as a fixed fault when a data corrected by an error detection and correcting means is taken as the error again and executing the processing correcting an error bit and copying it to an alternate memory at the interval of data processing. CONSTITUTION:The error detecting signal Sa of an error correcting code forming and check circuit 9 is fed to a memory controller 13 and an error detecting signal Sb is fed to a processor CP. The operation of the processor CP is executed not by the program of a main memory 3 but by a microprogram of the processor CP when the signal Sb is received. If an fixed fault occurs in the sub- blocks 3-1-1--39 of the main memory 3, the alternate memory 4 corresponding to the block takes over the block. Then, the location of a fixed fault bit is stored in a storage register group 5 corresponding to the blocks 3-1-3-4. When the block including the fixed fault is the 3-2-l, the information to be given to the block 3-2-l is copied to the alternate memory 4-2 as to all addresses of the block 3-2. In order to prevent the intermission of data processing during the memory alternate operation, the memory alternate operation is executed one by one word at the refresh of memory.
申请公布号 JPS59165300(A) 申请公布日期 1984.09.18
申请号 JP19830039674 申请日期 1983.03.10
申请人 FUJITSU KK 发明人 SAKAMOTO YASUHIKO
分类号 G06F12/16;G06F11/10;G06F11/20 主分类号 G06F12/16
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