发明名称 DECODER CIRCUIT
摘要 PURPOSE:To attain low power consumption by flowing a current to a selected decoder circuit only so as to flow sufficiently the current thereby attaining high speed. CONSTITUTION:A coincidence circuit 35 consists of a pnp transistor TR and resistors RE, RC in this example. The signal level of a row and a column output is selected that the pnp TR at the cross point is not turned on when one or both of the row and column is at the selected level but turned on when both the row and column are at the selecting level only. In setting an output level of a buffer circuit, only the pnp TR at the cross point between the selected row and column is turned on. The current flowing to the TR turned on depends on the signal level of the row and column and the resistor RE. Thus, the output of the selected coincidence circuit is at high level and the output of all other coincidence circuits is at low level.
申请公布号 JPS59165291(A) 申请公布日期 1984.09.18
申请号 JP19830037397 申请日期 1983.03.09
申请人 HITACHI SEISAKUSHO KK 发明人 HONMA NORIYUKI;YAMAGUCHI KUNIHIKO
分类号 G11C11/413;G11C11/34 主分类号 G11C11/413
代理机构 代理人
主权项
地址