| 摘要 |
PURPOSE:To perform fast Fourier transform arithmetic through an arithmetic circuit of simple constitution regardless of variation in the number of points of the arithmetic circuit by using selectors and a shift register which are standard logical circuits for address generation. CONSTITUTION:When 16-point fast Fourier transform FFT arithmetic is performed, a counter 1a supplies outputs 4a, 4b, 4c, and 4d of bits 2<0>, 2<1>, 2<2>, and 2<3> to selectors 9a, 9b, 9c, and 9d. The shift register 8, on the other hand, generates control outputs 10a, 10b, and 10c of bits 2<0>, 2<1>, and 2<2> for controlling selectors 9a-9d. The outputs 10a-10c of the register 8 are ''0'' in a pass 1 of the FFT arithmetic and the selectors 9a-9d select counter outputs 4b-4d, and 4a to obtain an output 6a. Then, the outputs of the register 8 are ''1'', ''0'', and ''0'' in a pass 2 and the selectors 9a-9d select the counter outputs 4b-4d, and 4a to obtain an output 6b. Similarly, outputs 6c and 6d are obtained from the selectors 9c and 9d. |
