| 摘要 |
PURPOSE:To process data at a high speed and in a simple constitution by sharing all interfaces on a common bus line by plural CPUs. CONSTITUTION:CPUs 1a, 1b, 1c and 1d having data processing functions are provided together with memories 2a, 2b, 2c and 2d respectively. Then interfaces 3a1-3a4, 3b1-3b4, 3c1-3c4 and 3d1-3d5 are connected to the CPUs 1a, 1b, 1c and 1d by bus lines 4a, 4b, 4c and 4d respectively, These lines 4a-4c are connected by the line 4d to form a common bus line 4, and a proper address is given to each of those interfaces 3a1-3a4, 3b1-3b4, 3c1-3c4 and 3d1-3d5 respectively. |
