发明名称 GAAS LOGIC INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce power consumption per a gate by controlling a DFET for a load by an input signal to turn the DFET ON-OFF and operating the DFET in a false complementary type. CONSTITUTION:When an input signal VIN is at a high level, an EFET 51 and a DFET 53 in a driver are turned ON, voltage 56a, 56b among drains and sources operates as limiters to gates in the EFET 51 and the DFET 53, and the flow-in of currents from the gates are inhibited. The drain potential of the DFET 53 is brought to approximately control voltage VSS, and applied to a gate in a DFET 52. On the other hand, when the pinch-OFF voltage of the DFET 52, the both terminal voltage of diodes 541, 542, voltage VSS, etc. are set under some conditions, the EFET 51 is turned ON and the DFET 52 is turned OFF when the signal VIN is at the high level. When the signal VIN is at a low level, the DFET 53 and the EFET 51 are turned OFF, and the DFET 52 is turned ON.
申请公布号 JPS59163858(A) 申请公布日期 1984.09.14
申请号 JP19830037501 申请日期 1983.03.09
申请人 KOGYO GIJUTSUIN (JAPAN) 发明人 IGAWA YASUO;HOUJIYOU AKIMICHI
分类号 H01L27/095;H01L27/08;H03K19/00;H03K19/0952 主分类号 H01L27/095
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