| 摘要 |
PURPOSE:To increase the transfer speed of data by reading selectively a desired data group out of the data on the continuous addresses and transferring the selected data group to a direct memory access controller. CONSTITUTION:A direct memory access (DMA) controller 4 gives a request to a CPU3 for evacuation of both address and data buses and checks the state of a transfer request signal TxRQ after receiving an answer signal BA. The waveform of the signal TxRQ is decided by a register pattern of an ROM5, and the address of a memory 6 is advanced by one and synchronously with a clock signal while the signal TxRQ is kept at ''1''. While a timing producing part 7 transmits a latch signal to a data latching part 8 while the signal TxRQ is kept at ''0'' and synchronously with the clock data. As a result, the data to be transferred when the latch signal is supplied is transmitted to an I/O part.
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