| 摘要 |
This analog-ditigal coder determines the coefficients ao . . . an in two stages: during the first stage, the generator processes voltages VR and VRi with i=1 to k-1; during the second stage, the generator processes the voltages VR and VRi with i=1 to n-k. A capacitive voltage divider (2kC, C) preceded by two sample and hold means (S3, C3, S4, C4) assures the division by 2k of the voltages processed during the second stage and their summation with the final voltage VR(k-1) produced during the first stage. |
