| 摘要 |
PURPOSE:To perform efficient transfer by detecting a request to send from a processor element (PE) by a T scanner, detecting a receivable PE by an R scanner, and transferring data from an originating PE to plural destination PEs. CONSTITUTION:A PE which requests data transmission sets a flag T, and the T scanner (TSC) 3 detecting it actuates a free bus controller (BC). The BC sends a signal to a switch network 5 in order to connect the port of the PE to a bus. Then, a code is transferred from the PE to the BC. The BC receiving the code sends an instruction for detecting a free PE to an R scanner (RSC) added to a PE group and sends a signal in order to turn on a bus receiver when a free PE is found. Consequently, the transfer path from the originating PE to the destination PE is formed, so individual data is sent and then the bus receiver is placed in a state WAIT. This process is repeated to acquire L units of PEs and bus receivers in the state WAIT are all turned on to transfer common data at a time. |
