发明名称 SEQUENTIAL PARALLEL TYPE ANALOG/DIGITAL CONVERTER
摘要 PURPOSE:To obtain an A/D converter and multiplier which works stably without increasing hard quantity by using sequentially parallel comparison type A/D converters in terms of time division. CONSTITUTION:An input analog signal Vin is compared with the comparison voltage by seven comparators 20. At first the reference voltage VREF and the earth potential are applied to both terminals 30 and 31 of a series capacitor train. Then the comparison voltage is generated from each juncture between capacitors. A switch is selected by an EXOR26 and an AND27 and on the basis of the first comparison result, and the electric charge is accumulated at a sampling/holding circuit 28. The reference voltage of the next stage is generated at the output terminals of integration circuits 29 and 29', and the comparison of the next stage is carried out. Then the reference voltage is generated in the same way, and the comparison is carried out for the 3rd and 4th stages. An A/D converter can be applied to a counter of a multiplier.
申请公布号 JPS59161917(A) 申请公布日期 1984.09.12
申请号 JP19830036414 申请日期 1983.03.05
申请人 TANAKA MAMORU 发明人 MIKI YUTAKA;CHIGUSA YASUTAMI;SHIMIZU NAOHIKO;TANAKA MAMORU
分类号 H03M1/14;H03M1/44 主分类号 H03M1/14
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