| 摘要 |
PURPOSE:To supply data with a long effective output time by shortening an operation period without waiting for an error detection result and correcting an error when necessary, and outputting data before and after the correction at different time. CONSTITUTION:Data consisting of a predetermined number of successive bits and a check bit 10 for error correction corresponding to the data are received. An UP error correcting circuit 1 outputs the data and data 11 equal to the check bit 10 as the 1st stage. An LOW-side error correcting circuit 2 outputs corrected data 12 in the 2nd stage. This output is selected by a selecting circuit 3 and a holding means 4 which holds its output 16 and the LOW-side error correcting circuit 2 are operated alternately to detect an error. When the error is detected, a selection signal 15 inputted to the selecting circuit 3 is delayed and the data after the correction is held by the holding means 4 to output an error correction response signal 17. |
