| 摘要 |
PURPOSE:To process an arithmetic of a registered memory, which is continued (n) times, at a high speed by 2n machine cycle, by executing an address calculation of an operand describing part before decoding an operation code of a machine language instruction and branching it to a macro-instruction group. CONSTITUTION:When executing an instruction of a form 2, one instruction is executed by four machine cycles by executing a decoding D of an operation code and an address calculation A of an operation describing part, in parallel by the same machine cycle. Also, when executing a form 1 (branch instruction), the address calculation A of the operand describing part is executed before the decoding D, and a main storage device address of a branch destination is calculated first. In this way, an instruction of the branch destination is read out by the following machine cycle, and one machine cycle is shortened comparing with the case when there is no branching.
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