发明名称 TIMING GENERATING CIRCUIT
摘要 <p>PURPOSE:To generate a timing signal whose 50% duty is stable, from a timing signal whose duty is unstable, by providing a means, etc. for detecting a duty from an input timing signal, etc. whose duty is varied. CONSTITUTION:A decoder, etc. for detecting a duty from an input timing signal whose duty is varied and a timing signal outputted from a waveform shaping circuit are provided. For instance, an input timing signal CLK whose duty is unstable and an output timing signal of this timing generating circuit are inputted to a decoder 7, and decoding outputs T1-T4 corresponding to a combination of each signal are generated and sent out to a duty controlling circuit 2. Subsequently, by a duty controlling circuit 2, voltage used for adjusting a duty is generated from the decoding outputs T1-T4, and by a duty adjusting circuit 3, charge and discharge are executed in accordance with the generated voltage, and the duty is adjusted. Thereafter, by a waveform shaping circuit 4, an output signal of the duty adjusting circuit 3 is shaped as to its waveform, and a timing signal is outputted.</p>
申请公布号 JPS59160221(A) 申请公布日期 1984.09.10
申请号 JP19830034978 申请日期 1983.03.02
申请人 MATSUSHITA DENKI SANGYO KK 发明人 WAKABAYASHI NAOKI;NISHIZAWA TEIJI
分类号 G06F1/04;H03K5/04 主分类号 G06F1/04
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