| 摘要 |
PURPOSE:To decrease the probability of delay in instruction read waiting decoding after branching by alllowing two times' share of branch destination instruction read of a branch instruction to have priority over other processings. CONSTITUTION:The branch instruction is executed at the beginning of a cycle and the 1st instruction is read including a head instruction of branch destination. Since an FF12 goes to 1 during the cycle 2, a selector 16 selects an output line 34 of a register 6 and a selector 17 selects a fixed value 8 respectively. Further, 8 is added to the branch destination address by an adder 5 and the result is stored in the register 6. The content of the register 6 is transmitted to a storage device 1 on an address line 14 at the beginning of the next cycle 3 and the 2nd read instruction of the branch destination is attained. On the other hand, since an output of an FF11 goes to 1 when the decoding of the branch instruction is finished, an AND of a gate 30 is established, and a signal line 32 goes to 0. Thus, a decoding start command of the succeeding instruction is suppressed by a gate 29 and the start of next decoding is suppressed during the 2nd instruction is read.
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