发明名称 TIME SWITCH CIRCUIT
摘要 PURPOSE:To reduce the power consumption of a time switch by connecting plural storage elements in parallel, inputting data only to a storage element specified by a selection signal and outputting data only from a storage element specified by a control signal, and inverting only one storage element in state during switching operation. CONSTITUTION:It is assumed that the pieces of control information 00, 01, 02, and 03 outputted from a control memory 3 are at an L, L, L, and an H in the 1st cycle, at the L, L, H, and L in the 2nd cycle, at the L, H, L, and the L in the 3rd cycle, and at the H, L, L, and the L in the 4th cycle. At this time, a data storage circuit 2 allows only a control storage element 23 to output data and places output terminals of other control storage elements in a high-impedance state in the 1st cycle. Only an element 22 outputs data in the 2nd cycle, only an element 21 outputs data in the 3rd cycle, and only an element 20 outputs data in the 4th cycle. Therefore, output data Dout to the outside are D, C, A, and B and their order is different from the order of A, B, C, and D during input, so they are outputted in the opposite order in this example.
申请公布号 JPS59158190(A) 申请公布日期 1984.09.07
申请号 JP19830031651 申请日期 1983.02.26
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 NIKAIDOU TADANOBU
分类号 H04Q3/52;H04J3/04;H04Q11/04 主分类号 H04Q3/52
代理机构 代理人
主权项
地址