| 摘要 |
PURPOSE:To detect a failure of a pipeline by suppressing the start of execution of arithmetic of succeeding instructions when an output of the 1st comparator detects dissidence and an output of the 2nd comparator detects coincidence. CONSTITUTION:The 1st comparator 19 compares the content of a control information registration register 17 to a preceding instruction with the content of a control information register 15 to produce and store the control information of pipeline for a succeeding instruction. The 2nd comparator compares the content of an address registration register 18 to a preceding instruction with the content of an operand address register 16 for the succeeding instruction. When the outpt of the 1st comparator 19 detects dissidence and the output of the 2nd comparator 20 detects coincidence, the start of execution of arithmetic of the succeeding instruction is suppressed.
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