| 摘要 |
PURPOSE:To prevent the collision of signals on a bus by inhibiting the data output from each board until the period in which a permitting signal, which opens the gate of a driver provided on each board connected to the tristate common bus, is stabilized. CONSTITUTION:Clock signals are inputted to two input terminals of an NAND gate 25, and a signal which is low-level in the first quarter of one machine time is obtained as the output and is inputted to an NAND gate 23 together with the permitting signal of a decoding circuit 24. When the low-level signal is inputted to a gate control input terminal of a tristate driver 20, the gate is opened, and data of a board 101 is transmitted to the common bus through a signal line 22, the tristate driver 20, and a signal line 21; and consequently, the gate is closed unless the permitting signal is high-level (for existence of output request) and a clock signal 3 is high-level (the latter three quarters of one machine cycle).
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