发明名称 MEMORY DEVICE HAVING DETECTING MEANS FOR REDUNDANT BIT
摘要 PURPOSE:To detect the use of a redundant bit as well as the position of a defective bit by applying the voltage higher than VCC to a part of an input terminal supplied from outside and checking the address input obtained when the current flowing to said input terminal is detected. CONSTITUTION:An input terminal 1 is kept under a high impedance state in a normal working mode. While the voltage higher than 8V is applied to the terminal 1 when the detection is desired for the position of a redundant bit. then a word line 10 is boosted up to the VCC level with selection of the redundant bit while MOS diodes 2-2'' are under a conduction state. Thus the gate of an MOSFET3 is charged through an MOSFET4, and this potential A is boosted by a signal which is set at a high level more slowly than a word line 6 by a boot capacity 5. Then the FET3 conducts, and a current flows to the VCC from the terminal 1.
申请公布号 JPS59157899(A) 申请公布日期 1984.09.07
申请号 JP19830030289 申请日期 1983.02.25
申请人 NIPPON DENKI KK 发明人 INOUE TAIICHI
分类号 G11C29/00;G06F11/00;G11C29/04;H01L27/10 主分类号 G11C29/00
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