发明名称 SHIFT CIRCUIT
摘要 PURPOSE:To keep the difference of delay with time between a parity bit and a data bit of an output data at the occurrence of parity to a small value by generating the parity bit at each byte of an output data. CONSTITUTION:A parity generating means 7 ORes exclusively paritity information of an output of a byte shift means 4 and an output of an exclusive OR means 6 and sets a parity bit in 8-bit to a data in 8-byte in the output of a data shift section 2. In this case, there are two methods to set the logical value of the data bit to 0 by the ineffective means 5 of the effectiveness of the parity information output from the byte shift means 4. As for the 1st method, the parity bit of output bytes 0-7 of the byte shift means 4 is used, and as for the 2nd method, the parity bit of 1-8 of the output bytes of the byte shift means 4 is used.
申请公布号 JPS59158438(A) 申请公布日期 1984.09.07
申请号 JP19830033281 申请日期 1983.03.01
申请人 NIPPON DENKI KK 发明人 SHIMODA WATARU
分类号 G06F7/00;G06F5/01;G06F7/76 主分类号 G06F7/00
代理机构 代理人
主权项
地址