| 摘要 |
PURPOSE:To speed up the supply of operand data by reading an operand data and an address from a buffer storing them when an instruction executed once is executed by the identical operand address again. CONSTITUTION:When an instruction processing execution unit 1 starts the decoding of an instruction, an address of the instruction is outputted on a signal line 101 and set to a register 11. An output of the register 11 is connected to a data buffer 20 and an instruction address of the data buffer 20 is searched by an address of the instruction set to the register 11. When an instruction address coincident with an address set to the register 11 exists in the data buffer 20, the corresponding data and operand address are outputted to a register 14. An output of the register 14 is transmitted to an instruction processing execution unit 1 on a signal line 104.
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