发明名称 CHANNEL SELECTING CIRCUIT OF PLL FREQUENCY SYNTHESIZER SYSTEM
摘要 PURPOSE:To avoid malfunction due to noise at AFT operation by placing priority over a signal applied earlier timewise when an AFT up signal and an AFT down signal are applied at the same time. CONSTITUTION:First it is discriminated whether the AFT signal is an up signal. When the signal is not the up signal, it is discriminatd whether or not the signal is a down signal. When the signal is not the down signal, the AFT operation is stopped. When it is the down signal, a local oscillating frequency fL is decreased sequentially and the frequency of an intermediate frequency signal SIF is lowered sequentially. It is discriminated whether or not the up signal exists in this state. When no up signal exists, the same state is continued and whether or not the down signal exists is discriminated when the up signal exists. When the down signal exists, the state that the frequency of the SIF is lowered sequentially is continued and when the down signal does not exist, the fL is increased sequentially and the frequency of the SIF is increased sequentially. Whether or not the up signal exists is discriminated in this case and the same state is continued when the down signal existis. When the no up signal exists, the AFT operation is stopped.
申请公布号 JPS59153319(A) 申请公布日期 1984.09.01
申请号 JP19830027347 申请日期 1983.02.21
申请人 SONY KK 发明人 ISHIGURO MEGUMI
分类号 H03J7/18;H03J7/28;H04N5/44 主分类号 H03J7/18
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