| 摘要 |
PURPOSE:To deliver the reproduction information even in a fast forward mode and at the same time to mute said reproduction information when noises are generated, by driving a resetting means and a muting means in response to a fact that the relation between read and write addresses does not satisfy the prescribed conditions to a memory. CONSTITUTION:A comparing means 14 which compares the relation between the write and read addresses, i.e., the outputs of counter 10 and 13 delivers pulses when both addresses get close too much to each other or away too much from each other. This pulse sets the counter 10 under an initial state, and the counter 10 starts counting the synchronizing signals. Then a flip-flop 16 is set and accordingly a counter 15 delivers the signal of a low level to close a gate circuit 7. A D/A converter 8 delivers continuously the output obtained at that time point, that is, the converter 8 is muted. At the same time, the counter 13 is reset by the set output of the flip-flop 16. The counter 15 counts 15 synchronizing signals, and the output of the counter 15 is inverted to a high level to reset the flip-flop. The gate 7 is also driven to apply the read data of an RAM5 to the converter 8. The muting state of the converter 8 is released. |
