发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To reduce the load of the signal which reduces a current for memory holding, by constituting a flip-flop with an inverter consisting of a programmable resistance element and an N-ch transistor TR and an inverter consisting of a P-ch TR and an N-ch TR. CONSTITUTION:When a polysilicone fuse POLY2 is not fused in a defective address registering circuit, a node N2 reaches the potential of a power source VCC more quickly than a node BOUT and the node BOUT becomes the earth potential after the power source VCC is turned on if R2C1<R4C2 is set with respect to circuit constant. Consequently, a DC current is not flowed to this circuit. When the polysilicone fuse POLY2 is fused, the node N2 is in the floating state of the earth potential before the power source is turned on, and the potential of the power source VCC is outputted to the node BOUT after the power source VCC is turned on. The earth potential connected to a power source GND with a low impedance is outputted to the node N2. Consequently, a DC current is reduced, and a control signal is not necessary.
申请公布号 JPS59152597(A) 申请公布日期 1984.08.31
申请号 JP19830025666 申请日期 1983.02.18
申请人 NIPPON DENKI KK 发明人 WATANABE TAKAYUKI
分类号 G11C29/00;G11C29/04;H03K3/286 主分类号 G11C29/00
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