| 摘要 |
The processor of the invention essentially includes a parallel calculating circuit 2 whose inputs X, Y and output P are each linked to a bus segment 4, 5, 6 forming part of bus 3 forming a closed loop divided into segments by bidirectional gates 7, 8, 9. This bus is linked to memories 15, 16, 17 and to input/output terminals 11-13. Application: signal processing. <IMAGE>
|
