发明名称 FORMING METHOD OF MULTILAYER INTERCONNECTION
摘要 PURPOSE:To prevent a foil from disconnecting and to improve the reliability of a semiconductor device using multilayer interconnection by forming a resist of lower layer wiring shape on a polycrystalline silicon layer, implanting the remaining polycrystalline silicon ions with the resist as a mask, and then oxidizing the entire polycrystalline silicon except the lower layer wiring forming portion and the surface of the polycrystalline silicon of the lower layer wirings. CONSTITUTION:After lower layer wiring-shaped resists 12, 12 are formed on a polycrystalline silicon layer 11, the layer 11 is etched in a lower layer wiring shape. With the resists 12, 12 as masks an impurity is implanted to the remaining layer 11 at the positions 13, 13 except the lower layer wiring forming portion. After the resists 12, 12 are removed, a heat treatment is executed, the layer 11 of the positions 13, 13 except the lower layer wiring portion is completely oxidized, the surface of the layer 11 of the lower layer wiring forming portion is oxidized, lower layer wirings 14, 14 and the second insulating film 15 to become an interlayer insulating film are formed. To improve the insulating withstand voltage of the upper and lower layer wirings 14, 14, a PSG film 16 is formed. Upper layer wirings 17 made of aluminum are formed on the film 16 to complete multilayer interconnection.
申请公布号 JPS59152644(A) 申请公布日期 1984.08.31
申请号 JP19830026474 申请日期 1983.02.18
申请人 SANYO DENKI KK 发明人 TANASE KENJIROU
分类号 H01L21/3213;H01L21/306 主分类号 H01L21/3213
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