发明名称 MAXIMUM/MINIMUM DETECTION CIRCUIT
摘要 PURPOSE:To enable the detection of generation and the magnitude of the maximum and minimum of a signal at a high speed by control two flip-flops sequentially according to the results of the comparison of sampled data to check changes in the gradient of an input signal. CONSTITUTION:Subtraction is done with a subtracter 3 between values of registers 1 and 2 into which sampled data are inputted sequentially and the results of the comarison between the absolute value of the results of the subtraction and a set value are held with a latch 6. After the operation of the comparator 5, values of the registers 1 and 2 are compared in the magnitude with a comparator 7 and the results are held with a latch 8. Then, a pulse is inputted into clock terminal of FFs 9 and 10 to transfer the contents of the FF9 to the FF10 and when an output of the comparator 7 is A>B, the FF9 is set while when A<B, it is reset. Then, outputs of the FFs 9 and 10 are inputted into a decoder 11. When the maximum or minimum is generated, the decoder 11 goes to logic ''H'' at output terminals respectively. At this point, the maximum or minimum value is outputted on a bus 20 by opening a gate circuit 12 connected to the register 2.
申请公布号 JPS59150346(A) 申请公布日期 1984.08.28
申请号 JP19830018844 申请日期 1983.02.09
申请人 TOSHIBA KK 发明人 HONMA NAOKI
分类号 G01M99/00;G01R19/04 主分类号 G01M99/00
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