| 发明名称 |
Dual gate CMOS transistor circuits having reduced electrode capacitance |
| 摘要 |
Dual gate P-channel and N-channel transistors are interconnected in various configurations to provide logic circuits such as inverters, NAND gates, NOR gates, and Exclusive-OR gates.
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| 申请公布号 |
US4468574(A) |
申请公布日期 |
1984.08.28 |
| 申请号 |
US19820374586 |
申请日期 |
1982.05.03 |
| 申请人 |
GENERAL ELECTRIC COMPANY |
发明人 |
ENGELER, WILLIAM E.;MAZIN, MOSHE |
| 分类号 |
H01L27/092;H03K19/0948;H03K19/21;(IPC1-7):H03K19/01;H03K19/09;H03K19/20 |
主分类号 |
H01L27/092 |
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