| 摘要 |
PURPOSE:To prevent the disorder of vertical synchronism even when an input TV signal is weak by making a phase comparison between vertical synchronizing pulses obtained by dividing the frequency of a clock generated by multiplying the horizontal synchronizing signal frequency of the input TV signal by an integer and the vertical synchronizing signal of the TV signal. CONSTITUTION:The TV signal inputted from a terminal IN is separated by a synchronizing separator circuit 2 into a horizontal synchronizing signal HS and a vertical synchronizing signal VS. The frequency of the signal HS is multiplied by an integer through a voltage-controlled oscillation circuit 1 to generate a clock hfH, which is inputted to a frequency dividing circuit 3 to generate vertical synchronizing pulses A. The waveform of the signal VS is shaped by a phase shifting circuit 4 to obtain a signal B. The signal obtained by inverting 7 a signal A is phase-compared by an NOR circuit 8, whose output is supplied to a shift register (SR) 5 through an NOR circuit 9. When the phase dissidence between the signals A and B is detected by specific times or more continuously, the output E of the SR5 goes up to a high level and the frequency divider 3 is reset by the signal B passed through NOR circuits 12 and 13; and then the signals A and B are put in a same phase and the stable signal A is outputted from a vertical driving pulse output circuit 14. |
