| 摘要 |
PURPOSE:To determine the memory arrangement of a system easily by dividing a plural memories into priority memories and non-priority memories, and during the access of the priority memories, sending an operation suppressing signal to the non-prior memories. CONSTITUTION:Three slave processors LP1-LP3 are connected to a bus B1 of a master processor GP through respective slave memories LM1-LM3. These memories LM1-LM3 have the capacity of about 64K bytes and about 16K bytes out of the 64K bytes constitute a common area to be accessed also from the master processor. The master memory GM has the capacity of about 1M bytes and can not be accessed from the slave processors. The master processor GP can access all the master memories. If accesses are competed in a part where one of the slave memories LM1-LM3 is overlapped to the master memory GM, an LMBSY signal is generated in order to allow the slave processor to access with priority, so that the access from the master processor is inhibited. Consequently, a memory can be determined and changed simply without considering the mounting or nonmounting of other memories. |
