| 摘要 |
PURPOSE:To reduce the number of wirings and elements by detecting all outputs of a unit stage to be reduced to logical 1 and an output of the unit stage closer to the MSB in the unit stages to be reduced to logical 0 in binary outputs detected by a binary up-counter. CONSTITUTION:Assuming that a level of a set terminal is logical H before a time t0 and a preset data (111000) is set to each unit stage; then an output level of an NAND gate 15 goes also to H. When the level of the set signal moves to L at the time t0, the binary up-counter counts a clock signal. When the binary output of the counter goes to (001011), the detected gate output goes to L and further, when the binary output goes to (001100), the detected gate output goes to H and the detection is completed.
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