发明名称 LOGICAL LSI CAPABLE OF INVERTING OUTPUT LEVEL
摘要 PURPOSE:To save a test time required for the generation of a complicated input pattern and a main pattern necessary for the switching of an output logical level by switching the output logical level at measurement by one input pin provided separately. CONSTITUTION:An LSI 1 has a logical circuit section 2 in its inside, input pins IN1-INn are connected to the outside of the LSI and input signals I1-In are inputted thereto. Signals S1-Sn of the circuit 2 are fed respectively to one input of exclusive OR gates G1-Gn, and an output of the gates G1-Gn is fed to output pins OUT1-OUTn of each LSI. In measuring an output level of the LSI1, a suitable DC level is given to the input pins IN1-INn, a low potential signal is supplied to an inverting input pin NT at first and the output level of output pins OUT1-OUTn. Then, a high potential signal is supplied to the pin NT to invert the output level of the OUT1-OUTn, allowing to measure both low and high potential levels.
申请公布号 JPS59147540(A) 申请公布日期 1984.08.23
申请号 JP19830021447 申请日期 1983.02.14
申请人 HITACHI SEISAKUSHO KK 发明人 NAKAZAWA KIKUO
分类号 H03K19/00;H01L27/04;H03K19/0175 主分类号 H03K19/00
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