| 摘要 |
<p>Memory bank selection is provided in a pipeline architecture computer system by monitoring the address bus for an address indicative of a program instruction such as a jump to subroutine (JSR) requiring the presence of a memory address on the data bus, and then latching at least portions of the memory address when on the data bus. The latched portions of the address are decoded for memory selection, and an enable signal is then generated and applied to enable the selected memory.</p> |
