| 摘要 |
PURPOSE:To improve the operation speed, by executing the operation control and the loop control independently of each other. CONSTITUTION:By the execution of a loop set instruction, the first operand is stored in a loop final address storage register 5. The second operand is stored in a loop counter 3, and the third operand is stored in a branch destination address storage register 2. Then, an address coincidence detector 4 becomes operation state. The detector 4 checks always the coincidence between contents of a counter 1 and the register 5 and counts down the value of the loop counter 3 by one if they coincide with each other. When the result is not zero, the output of the branch destination address register 2 is set to the counter 1 to execute the loop. Since the instruction in the loop final address can be executed in an operation processing part 6 during this operation, the loop control and the operation processing are executed in parallel. |
