发明名称 |
PARALLEL SIGNAL PROCESSOR |
摘要 |
PURPOSE:To perform picture signal processing on real-time basis by writing a signal alternately in memories of two systems consisting of plural memory blocks, and reading their contents and outputting them after serial conversion. CONSTITUTION:Input data inputted to a register 10 is inputted to a memory 2 or 3 through a latch 12 and a multiplexer 13. The memory 2 consists of memories 2-1-2-21 and input picture data is inputted to the memories 2-1-2-21 in parallel. In case of the memory 3 it is the same. Picture data written in the memory 3 is read out in parallel while the input picture data is written in the memory 2, and sent in series to a processor 1 through a parallel/series conversion register 7. This register 7 reads the contents of the memory at a low speed which is a submultiple of that of the instruction cycle of a processor 1. The contents of the register are inputted to the processor, one by one in every instruction cycle. |
申请公布号 |
JPS59146363(A) |
申请公布日期 |
1984.08.22 |
申请号 |
JP19830020661 |
申请日期 |
1983.02.10 |
申请人 |
MATSUSHITA DENKI SANGYO KK |
发明人 |
YAMADA HARUYASU;HASEGAWA KENICHI;MORI TOSHIKI;AONO KUNITOSHI |
分类号 |
G06F15/16;G06F15/80;G06T1/20 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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