发明名称 DESIGNING METHOD OF CIRCUIT PATTERN IN UVPROM
摘要 PURPOSE:To determine a timing signal for a circuit and the holding time of potential without considering the effect of beams by coating a diffusion layer region, in which some potential must be kept for a fixed time under the state separated from others in a circuit shape, with a substance having non-transmitting property to beams. CONSTITUTION:Electron-hole pairs are not generated by the effect of beams due to no-strike of beams because an N<+> diffusion layer region 11 is coated with an Al region section 17 reflecting beams. Consequently, the value of junction leakage is represented by a theoretical value even in an integrated circuit containing a UVPROM. Quite the same circuit system as a memory storage using a normal metallic cap can also be used even in an integrated circuit, at least one part thereof contains the UVPROM.
申请公布号 JPS59145575(A) 申请公布日期 1984.08.21
申请号 JP19830020128 申请日期 1983.02.09
申请人 NIPPON DENKI KK 发明人 HASHIMOTO KIYOKAZU
分类号 H01L27/112;H01L21/8246;H01L21/8247;H01L29/788;H01L29/792 主分类号 H01L27/112
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