| 摘要 |
PURPOSE:To prevent the competition for a bus among plural processors with a simple circuit by applying all OR outputs of shared bus use permission signals to the input of an FF and applying the shared bus use permission signal of each processor as the set input of the FF. CONSTITUTION:When a use request signal REQ1 of a shared bus attains to H- level, the signal REQ1 is outputted from an NAND gate as it is because the output of a D-FF 8 is in the H level when it is possible to use the shared bus, and this signal attains to an L-level shared bus use request signal BREQ1. Since this signal is connected to a bus request input terminal BREQ of a processor 7, and L-level signal BACK1 is outputted from a bus use permission output terminal BACK of the processor 7 after a certain timing. This signal is applied to a NOR gate 12 and the set input of the FF 8, and an output Q of the FF 8 goes to H-level. Meanwhile, the output of the gate 12 goes to L-level. Consequently, since L-level outputs Q of D-FFs 10 synchronized by clocks phi2-phin are applied to the input of a NAND gate 11, these request signals are inhibited. |
