| 摘要 |
PURPOSE:To obtain a data pass control system with high efficiency and high reliability by transmitting only the data including a data packet or the parts before and after said data packet to the next station when the data is transmitted over the stations in a loop or bus form cascade connection. CONSTITUTION:If a false header X emerges before a real data packet for the output of a shift registe 20; a decoder 21 outputs a wrong header detection pulse N'2 in the form of a signal DSDT. Then a flip-flop 23 is set at a high level. Meanwhile, the pass data passed through an AND gate 32 is supplied to a memory 25. However, a pulse N2 is outputted when the header of a real data packet is supplied. An RS flip-flop 23 is kept at a high level, and the signal DSDT or FTDT is applied with OR through an OR gate 31 and is supplied to a clear terminal of the memory 25. Thus the data is cleared. In such a way, only the real data packet passes through stations. |
