| 摘要 |
An address converting and generating system for an information processing system is disclosed. The address converting and generating system includes a segment type memory and an instruction having an operation code part, a field for specifying a register for loading a physical address representing a segment relative address, and a displacement for specifying a logical address. This instruction is decoded by an instruction decoder, and the physical address is generated from the logical address by referring to a segment table directory and a segment table. The generated physical address is loaded, together with a segment base address, a segment table number, and a segment table entry, in a register specified by the register specifying field. An effective address is generated by addition of the contents of the specified register and the address specified by the displacement. The system further has an instruction for generating a logical address from a physical address. When this instruction is executed, the segment base address is subtracted from the physical address. The subtraction result, the segment table number and the segment table entry are combined to provide the logical address which is loaded in the register specified by the register specifying field of the instruction.
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