| 摘要 |
PURPOSE:To eliminate assuredly the collision of read/write and refresh request by providing a circuit which converts the priority for reception of the normal memory read/write request and the refresh request to a dynamic memory. CONSTITUTION:This circuit is formed by adding gates 21-24 to a conventional refresh control circuit. When the memory request of MRQ0 and MRQ1 are produced consecutively and a refresh request MRQFE is kept waiting until 58T, the output of the gate 21 is set at ''0''. At the same time, MRQ0, Q1 and Q2 are inhibited by gates 22-24 respectively, and the MRQREF is forcibly accepted. Then the refresh is assuredly carried out within tREF. The tREF is a refresh time permitted at every row address. In this example, tREF covers 0T-60T. Then memory cycle needs 2 clocks and therefore has about 30 memory cycles. |
