| 摘要 |
PURPOSE:To reduce the arithmetic quantity by using a circuit which controls the tap coefficient of each sample value for every plural sampling cycles. CONSTITUTION:The sample signal having sample value xi is applied to plural cascaded delay elements 2+N-2-N+1 having the delay time of sampling cycle respectively. A tap coefficient control circuit consisting of multipliers 3+N- 3-N and 9+N-9-N and subtractors 10+N-10-N is provided at the input/ output part of each delay element. The output of each tap coefficient control circuit is added through an adder 4, and the automatically equalized output signal yn is delivered. A part of the signal yn is discriminated by an identifying circuit 6, and the discriminated identifying signal yD is delivered. A subtractor 7 obtains the difference between signals yn and yD, and the output of the subtractor 7 is multiplied by a coefficient (g) through a multiplier 8. The output of the multiplier 8 is distributed alternately to lines 5-1 and 5-2 every sampling cycle by a switch circuit 5. The signals distributed to lines 5-1 and 5-2 are multiplied by even and odd number multipliers 9 of the tap coefficient control circuits. |
