发明名称 MICROPROCESSOR SYSTEM
摘要 <p>PURPOSE:To enable the titled system to possess commonly the same memory at the same time and to enable two MPUs to operate at a maximum speed independently by shifting clock signals of two microprocessor MPUs in phase by 180 deg.. CONSTITUTION:Outputs phi1, phi2 of a clock generator 15 are connected to the first MPU 14 as they are, and inverted signal outputs of outputs phi1, phi2 are connected to the second MPU 16. To make a program effective starting address at the time of turning on of a power source different in address at MPU 14 and MPU 16 and make them execute special operation, the uppermost bit for the address line 21 of the second MPU 16 is inverted by an inverter 20, and connected to an address bus 22. Addresses of ROMs 17, 18 and a RAM input/output device 19 are arranged different in address for MPU 14 and MPU 16. Practically, however, the arrangement of the same memory and the same input/output device on the same bus is made possible.</p>
申请公布号 JPS59139470(A) 申请公布日期 1984.08.10
申请号 JP19830012313 申请日期 1983.01.27
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SHIMIZU YOSHIKAZU
分类号 G06F15/16;G06F1/04;G06F1/10;G06F13/16;G06F15/177 主分类号 G06F15/16
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