发明名称 MASTER AND SLAVE CLOCK DEVICE
摘要 PURPOSE:To increase a mean supply current sent out of a master clock and increase electric power supply to a slave clock by transmitting auxiliary pulses additionally during a stop period of clocking pulses transmitted from the master clock to the slave clock. CONSTITUTION:This master and slave clock device has the master clock 1 and slave clock 4 and transmits auxiliary pulses which has a pulse crest value or pulse width less than that of clocking pulses additionally during the stop period of clocking pulses sent out of the master clock 1. The slave clock 4, on the other hand, extracts the sent clocking pulses by a voltage comparator 6, and transfers them to a counter 7 and also applies the composite signal of the clocking pulses and auxiliary pulses to a rectifying and smoothing circuit 11. The rectifying and smoothing circuit 11 converts the composite signal into a DC voltage, which is supplied as a power source to respective circuits 7-9 constituting the slave clock.
申请公布号 JPS59138978(A) 申请公布日期 1984.08.09
申请号 JP19830014156 申请日期 1983.01.31
申请人 MATSUSHITA DENKO KK 发明人 KURODA GIICHI;GOTOU KAZUHIKO
分类号 G04G9/00;G04G19/02;G04G99/00 主分类号 G04G9/00
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