| 摘要 |
PURPOSE:To reduce parasitic capacitance largely by simple structure, and to increase the number of resistors loaded by arranging a high permittivity porcelain capacitor part to an uppermost layer, a low permittivity porcelain material substrate to an intermediate layer and a bus wiring substrate to a lowermost layer. CONSTITUTION:An annular spacer 13 interposed between a laminated porcelain capacitor part 1 and a porcelain material substrate 15 is constituted by a porcelain material of low permittivity such as alumina. An electrode 12 is connected to an electrode 11 for the laminated porcelain capacitor part 1 by an electrode 14 on the space 13. An electrode 2 is not in contact with the procelain capacitor part 1 of high permittivity because the spacer 13 is interposed, and parasitic capacitance is not generated. The laminated porcelain capacitor part 1, the spacer 13 and the porcelain material substrate 15 are bonded firmly with adhesives 16 such as glass while an IC chip 5 is sealed in a closed space surrounded by these three parts. |
