| 摘要 |
PURPOSE:To lower the pinch-off voltage of a J-FET without reducing the dielectric resistance of an N-P-N transistor by normally making the thickness of an epitaxial layer in a J-FET forming region thinner than an N-P-N transistor forming region. CONSTITUTION:An N<+> type buried region 2 is formed to a P type substrate 1, an N type epitaxial layer 3 is grown on the substrate 1, and a P<+> type insulating isolation region 4 is formed from the layer 3 in order to electrically insulate each element. The surface of an epitaxial layer 10 in a region in which a J- FET must be formed is removed through etching. A P type gate region 11 in the J-FET and a P type base region 12 in an N-P-N transistor are formed. Each contact region is formed through a known method. |
