发明名称 MULTIPLICATION SYSTEM
摘要 PURPOSE:To reduce the number of times of accessing to a memory for an arithmetic system of multiplicand and multiplier of pack type by providing a register to store the results of operations for plural digits of the multiplicand and multiplier respectively. CONSTITUTION:A buffer BF0 fetches the multiplicand and multiplier by one byte one out of a memory like ab, ef, etc. Then the 10th digit is obtained by an adder ADD1 from two buffers BF1 set in the middle course and via a multiplier ML. In addition, the 1st and 10th digits are decided by an adder ADD2 with a result store buffer BF2 for the lower digits. The 100th and 1,000th digits are decided by an adder ADD3. The result of operations is obtained at a buffer BF3 and then stored temporarily in the memory. Then (cdXef) is calculated, and the 1st and 10th digits of the preceding arithmetic results and the 100th and 1,000th digits of the new arithmetic results are stored in a buffer BF5 via the ADD3. Then the 100th and 1,000th digits of the preceding arithmetic results supplied from a carry buffer CB and the memory are stored in a buffer BF7 via an adder ADD4.
申请公布号 JPS59135544(A) 申请公布日期 1984.08.03
申请号 JP19820234673 申请日期 1982.12.27
申请人 FUJITSU KK 发明人 SAKURAI MITSUO;SASOU HIDEYUKI;SATOU NOBUYOSHI
分类号 G06F7/496;G06F7/491;G06F7/508;G06F7/52;G06F7/527 主分类号 G06F7/496
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