发明名称 INTER-PROCESSOR COMMUNICATION SYSTEM
摘要 PURPOSE:To improve the communication efficiency between processors by connecting a memory switching circuit connected to two pairs of memory circuits to the master and slave microprocessor units. CONSTITUTION:A pair of microprocessor units 10 and 20 are connected in 1:1 to memory circuits 30 and 40 respectively, and independent writing actions are applied to the circuits 30 and 40 connected with the inter-processor communication data. A switch request signal is sent to a gate switching circuit 51 in response to the switching decision of the unit 10. Thus the units 10 and 20 confirm that no access is given yet to the circuits 30 and 40 through signal buses (a) and (c) and then actuate gate circuits 52 and 53 through switch signal lines (d) and (f). Then the connection is given between the unit 10 and the circuit 40 as well as between the unit 20 and the circuit 40. Thus it is possible to read out the data which is written by the unit of the remote side to each other. Therefore it is avoided that both microprocessor units give a simultaneous access to a single memory circuit to generate a competition. This improves the efficiency for communication between processors.
申请公布号 JPS59135566(A) 申请公布日期 1984.08.03
申请号 JP19830010275 申请日期 1983.01.25
申请人 NIPPON DENKI KK 发明人 YAMADA KENJI
分类号 G06F15/167 主分类号 G06F15/167
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