发明名称 ADDRESS GENERATING MECHANISM
摘要 PURPOSE:To generate easily an address when an access is given to the two- dimensional data such as the image data stored in a memory by generating successively addresses in two stages. CONSTITUTION:The data Ak,1 set at a CAR10 is delivered to an output signal line 11 of address as the first address when the initialization is over. The data Ak,1 of the CAR10 is added 21 with data 1 of REGs 2 and 20. This result of addition is delivered to the line 11, and at the same time the values of CNTs 1 and 14 are counted up. This operation is successively repeated to deliver a signal showing that the final address in a block is delivered to a signal line 16. Thus the address output is over with the 1st block. In the same way, the address of the (n+1)-th block is delivered. Thus the values of CNTs 2 and 26 are set at (n+1) and coincident with the values of REGs 4 and 25. Then a signal showing a final block is delivered to a signal line 28. In such a way, the addresses to a two-dimensional image data are successively delivered with one line defined as one block.
申请公布号 JPS59135560(A) 申请公布日期 1984.08.03
申请号 JP19830010125 申请日期 1983.01.25
申请人 MITSUBISHI DENKI KK 发明人 KAMEYAMA MASATOSHI;MARUYAMA HIROYOSHI;KAZAMA SEISUKE
分类号 G06F12/00;G06F12/02;G06F13/00 主分类号 G06F12/00
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