发明名称 LOCK CONTROL SYSTEM OF MAIN MEMORY
摘要 PURPOSE:To reduce the deterioration of performance of a lock control system by preventing previously the transmission of a reference request from a processor to the region of a main memory which is locked by another processor. CONSTITUTION:A task selection circuit 6 transmits a reference address to a main memory 3 via a signal line 10 for reference of a header of the start queue or a control block. In this case, the reference address on the line 10 with the address of a control block or a header on a signal line 13 through a comparator 5 if the lock signal on a signal line 9 is set at (1). The coincidence or the discordance of the comparator 5 is informed to the circuit 6. When the coincidence is obtained, it means that an arithmetic processor 1 is referring or will soon refer the header or the control block to which the circuit 6 is going to refer. In such a case, the circuit 6 does not set the reference request on a signal line 11 at (1) and starts selection of another I/O task. If the lock signal on the line 9 is set at (0), the comparator 5 delivers a discordance signal to a signal line 15. Therefore the circuit 6 sets the reference request on the line 11 at (1) and starts the reference to the header or the control block on the memory 3.
申请公布号 JPS59135562(A) 申请公布日期 1984.08.03
申请号 JP19830010374 申请日期 1983.01.25
申请人 HITACHI SEISAKUSHO KK 发明人 TAKEDA KATSUMI
分类号 G06F12/00;G06F9/52;G06F13/16;G06F15/16;G06F15/177 主分类号 G06F12/00
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