发明名称 CONTROLLING SYSTEM OF AUTOMATIC DATA RECEIVING
摘要 PURPOSE:To cope with different transmitting speeds by a simple data receiving controlling circuit by discriminating the transmitting speed based on the interval of changing point of the 1st bit of receiving data different from the transmitting speed and sampling the receiving data by a timing pulse corresponding to the speed. CONSTITUTION:A transmitting speed discriminating circuit 7 measures the interval of time change of the initial bit of a receiving data and discriminates the transmission speed. A timing pulse generating circuit 8 is controlled by selecting one of bit interval widths (stored in advance) corresponding to plural transmitting speeds. The circuit 8 generates a timing pulse train suitable to the transmitting speed and outputs a timing pulse train suitable to the receiving data signal by the control of the discriminating circuit 7. A bit memory 9 samples the receiving signal by this pulse and stores the data for one word's share. The end of one word is informed to the circuits 7, 8 and the data in the memory 9 is outputted via a correcting circuit 11 in response to the substantial code form.
申请公布号 JPS59134947(A) 申请公布日期 1984.08.02
申请号 JP19830008815 申请日期 1983.01.24
申请人 NIPPON DENKI KK 发明人 MAKINO AKITOSHI
分类号 H04L29/08;G06F13/00;H04L13/18 主分类号 H04L29/08
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