发明名称 METHOD AND DEVICE FOR FORMING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce the size of a chip and to enhance a yield by handling a remaining circuit as a logic super LSI having circuit functions except a defective circuit if the remaining circuit operates normally even if part of the LSI has a defect and using in combination with another logic super LSI which performs insufficient circuit function. CONSTITUTION:The internal circuit of a logic super LSI chip 1 is divided into two circuit blocks 2, 3 having the prescribed functions, and an output signal of the block 2 to be inputted to the block 3 and logically processed by the block 2 is always once led out to terminals 4, 5 on the chip 1. In order to further allow the block 3 to logically process with the external wirings, terminals 6, 7 are provided on the chip 1. Similarly, an output signal to be similarly logically processed by the block 3 and to be inputted to the block 2 is similarly handled. When thus constructed, the chip 1 is inspected by an electric probe, and if any block is improper, it is supplemented by another block.
申请公布号 JPS59134864(A) 申请公布日期 1984.08.02
申请号 JP19830007223 申请日期 1983.01.21
申请人 HITACHI SEISAKUSHO KK 发明人 IKUZAKI KUNIHIKO
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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